This invention relates to a data-transfer controlling system, and more particularly to a system for transferring data between transmitter/receiver units connected to a common bus in which the number of conducting lines included in the common bus is reduced or the processing time for a transmitter/receiver unit to occupy the common bus is shortened.
In general, a data-transfer controlling system includes a plurality of transmitter/receiver units, such as processors, memory devices, input-output devices, etc, commonly connected to a common bus, and also includes a bus-control unit, which unit controls the signals of the transmitter/receiver unit requiring data transfer to be allowed or not allowed on the common bus. This control of allowing or not allowing the signals on the bus is usually executed during the time when a previous data transfer is effected between the transmitter/receiver units. In order to control the signals allowed on the common bus, the common bus in the prior art usually includes signal lines as follows:
a Transfer-Request Signal Line (REQ), PA1 b Permission-Signal Line (PRM), PA1 c Acknowledge-Signal Line (ACK), PA1 d Busy-Interlock Signal Line (BSY), PA1 e Transfer-End Signal Line (END), and PA1 f Data/Address Signal Line (D/A).
However, for the purpose of simplifying the control and decreasing the cost of the common bus, it is desirable to reduce the number of signal lines in the common bus.
In addition, in the prior art system, the permission signal is transferred one after another through transmitter/receiver units connected in series, to a transmitter/receiver unit which has been providing a transfer-request signal. Therefore, due to the delay time of each transmitter/receiver unit, a relatively long time is required to reach the desired transmitter/receiver unit when a relatively large number of transmitter/receiver units are connected between the bus-control unit and the desired transmitter/receiver unit.